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Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
Programming Specification
PS009201-0301
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(c) 2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top-Level Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OTP Memory Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3 3 5
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Unlock Sequence into EPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 EPROM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Top Level Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 EPROM Array Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Option Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-Down Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 EPROM I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommendations to Third-Party Programmers . . . . . . . . . . . . . . . . . . . . . Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 26 31 32
Third Party Developer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Top-Level Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 2 18-Pin DIP/SOIC Pin Configuration, STANDARD Mode . . . . . . . . . . 3 18-Pin DIP/SOIC Pin Configuration, EPROM Mode . . . . . . . . . . . . . 3 20-Pin SSOP Pin Configuration, STANDARD Mode . . . . . . . . . . . . . 4 20-Pin SSOP Pin Configuration, EPROM Mode . . . . . . . . . . . . . . . . 4 Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Top Level Operations Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 EPROM ARRAY READ/WRITE Mode Entry Functional Timing . . . 11 EPROM ARRAY READ Mode Functional Timing . . . . . . . . . . . . . . 13 EPROM ARRAY PROGRAM AND VERIFY Functional Timing . . . . 15 OPTION BIT PROGRAM AND VERIFY Mode Entry Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 OPTION BIT PROGRAM AND VERIFY Functional Timing . . . . . . . 19 OPTION BIT READ Mode Functional Timing . . . . . . . . . . . . . . . . . 21 Power-Down Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Z86E0x EPROM ARRAY and OPTION BIT PROGRAM AND VERIFY Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Z86E0x Additional Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . 25 EPROM ARRAY PROGRAM, VERIFY, and READ Algorithm . . . . 27 EPROM ARRAY READ Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OPTION BIT PROGRAM, VERIFY, and READ Algorithm . . . . . . . . 29 OPTION BIT READ Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Third-Party Top-Level Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Output Parallel Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Input Parallel Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 EPROM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-On Reset Pin Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Unlock Sequence Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mode Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 EPROM ARRAY READ/WRITE Mode Entry Conditions . . . . . . . . . 11 EPROM ARRAY READ Mode Conditions . . . . . . . . . . . . . . . . . . . . 13 EPROM ARRAY PROGRAM AND VERIFY Mode Conditions . . . . 15 Option Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions . . . 17 OPTION BIT PROGRAM AND VERIFY Mode Conditions . . . . . . . 20 Power-Down Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Z86E0x Additional Timing Specifications . . . . . . . . . . . . . . . . . . . . 25
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General Description
The EPROM Programming interface is a byte-wide data interface with 7 control inputs and a 17-wire connection. This document describes the EPROM interface pertinent to the following parts:
Z86E02 SL1995 Z86E04 SL1995 Z86E08 SL1995 Z86E09 SL1995
Top-Level Programming
After powering up, the programming sequence begins by sending the unlock code sequence, followed by the mode selection. The program address must be reset to 0000h after entering EPROM mode. The first data byte to be programmed is then loaded on Port 2. When the programming control sequence is applied, the programming pulse commences. Data is then verified for correct programming. If the data is incorrect, a count begins to record the number of programming pulse cycles before success is finally achieved. If the data is not programmed after NMAX attempts, it is a failed part. If data is verified, then it must be overprogrammed for a minimum of 3 times the cumulative programming time. The address counter is then incremented to the next address. The next data byte is sent, and programming continues using the same basic algorithm. See Figure 1.
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Figure 1. Top-Level Programming Sequence Start
Power-On Reset
Send Unlock and Mode Codes
Program Data at Set Address
Up to NMAX times
Next Address
Verify Data at Set Address
Pass
Fail
Overprogram at Set Address
Last Address
Verify Data at All Addresses
Last Address
Fail
Stop
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Parallel Programming Interface
The EPROM interface is a 17-wire connection. Review the part-specific pin diagrams in Figures 2 through 5 for part pin-out.
Pin Diagrams
Device pin-out diagrams for the 18-pin DIP/SOIC and 20-pin SSOP are shown in Figures 2 through 5. There are two configurations for the 20-pin SSOP device-- the corresponding parts are identified in the diagrams.
Figure 2. 18-Pin DIP/SOIC Pin Configuration, STANDARD Mode
18 17 16 15 14 13 12 11 10
P24 P25 P26 P27 VCC XOUT XIN P31 P32
1 2 3 4 5 6 7 8 9
P23 P22 P21 P20 GND P02 P01 P00 P33
Figure 3. 18-Pin DIP/SOIC Pin Configuration, EPROM Mode
D4 D5 D6 D7 VCC NC
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
D3 D2 D1 D0 GND PGM CLOCK CLEAR VPP
CE OE
EPM
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Figure 4. 20-Pin SSOP Pin Configuration, STANDARD Mode
P24 P25 P26 P27 VCC VCC XOUT XIN P31 P32
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
P23 P22 P21 P20 GND GND P02 P01 P00 P33
Figure 5. 20-Pin SSOP Pin Configuration, EPROM Mode
D4 D5 D6 D7 VCC VCC NC CE OE EPM
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
D3 D2 D1 D0 GND GND PGM CLOCK CLEAR VPP
Tables 1 and 2 indicate the device's Port 2 input and output EPROM data.
Table 1. Output Parallel Byte Bit Number Port 2 Output EPROM data 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
Table 2. Input Parallel Byte Bit Number Port 2 Input EPROM data 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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OTP Memory Size
The device is offered in 4 memory configurations. Table 3 lists the available sizes of EPROM memory.
Table 3. EPROM Size Devices Z86E02 Z86E04 Z86E08 Z86E09 Memory Size 0.5 KB 1.0 KB 2.0 KB 4.0 KB Last Address
01FFh 03FFh 07FFh 0FFFh
Device Operation
The device must first be unlocked before it can enter EPROM mode. Otherwise, the device remains in STANDARD mode. The device cannot be programmed in STANDARD mode. It can only be programmed in EPROM mode. The following sequence details the unlock procedure.
Unlock Sequence into EPROM Mode
The following unlock sequence is valid for all parts. Note: Unlock clock cycles are the XIN clock cycle entered by the programmer, not the internal Z8 SCLK cycles. 1. A POR must be completed before unlock operations begin. The XIN pin must be in a VIL state. Allow 50 ms minimum for the device to completely exit POR to allow the internal signal IRESET to go Low. See Table 5 for POR conditions. 2. Any time after POR, when the internal signal IRESET is Low. The unlock sequence can be sent. See Figure 6 and Table 4. 3. While the XIN pin is in a VIL state, force Port 2 pins with A5h. 4. Apply one clock pulse to XIN. The clock pulses should be a minimum of 1sec in duration. 5. Force the Port 2 pins with 5Ah. 6. Apply one clock pulse to the XIN pin. 7. Force the Port 2 pins with A5h.
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Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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8. Apply one clock pulse to XIN. 9. Force the Port 2 pins with F0h. 10. Apply one clock pulse to XIN. 11. Force the Port 2 pins with 0Fh. 12. Apply one clock pulse to XIN. 13. Force the Port 2 pins with 00h. 14. Apply one clock pulse to XIN. 15. Force the Port 2 pins with F1h. 16. Apply one clock pulse to XIN. 17. Force the Port 2 pins with 00h. 18. Apply one clock pulse to XIN. 19. The part is now in EPROM mode. The only way to exit EPROM mode is to perform a POR. Note: All signals must be stable before the XIN (CE) pin is pulsed High and cannot change until XIN (CE) pin is in a VIL state. The signal should be stable for a minimum of 1sec.
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Figure 6. Unlock Sequence
IRESET VCC CLEAR EPM X IN (CE) VPP CLOCK OE PGM Port 27 Port 26 Port 25 Port 24 Port 23 Port 22 Port 21 Port 20 XOUT
5V 0V VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL
1
No Connection
Note: 1. The device enters EPROM mode at this point when XIN goes Low.
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Table 4. Unlock Sequence Conditions EPROM Signal D0-D3 D4-D7 GND VCC CE (XIN) NC (XOUT) OE EPM VPP CLEAR CLOCK PGM 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 Pin 7 Pin 6 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Pin 8 Pin 7 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Forced State See Figure 6 See Figure 6 GND 5V See Figure 6 No Connection VIH VIH VIL VIL VIL VIH
Table 5. Power-On Reset Pin Conditions EPROM Signal D0-D3 D4-D7 GND VCC CE (XIN) NC (XOUT) OE EPM VPP CLEAR CLOCK PGM 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 Pin 7 Pin 6 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Pin 8 Pin 7 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 State GND GND GND Ramp to 5V GND No Connection GND GND GND GND GND GND
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EPROM Modes
The device offers two modes of operation. Table 6 lists the available mode options.
Table 6. Mode Selections Value Description A B EPROM Array Read and Write modes Option Bit Program and Verify modes
Top Level Operations
Figure 7 illustrates the operations available to the user after the device is unlocked and enters EPROM mode.
Figure 7. Top Level Operations Flow
Start
Power-On Reset to 5.0V
Unlock Sequence into EPROM Mode
EPROM Mode Selection
Exit
EPROM ARRAY READ/WRITE Mode
OPTION BIT PROGRAM/VERIFY Mode
Execute Power Down Sequence
Program/Verify/ Overprogram Operation
READ Operation
Program/Verify/ Overprogram Operation
READ Operation
End
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EPROM Array Modes
EPROM ARRAY READ/WRITE Mode Entry 1. To enter EPROM ARRAY READ/WRITE mode, all pins must be set as per Table 7. 2. EPM is lowered to VIL. 3. OE is lowered to VIL. 4. The VPP is raised to VIH. 5. The CLEAR is pulsed High to VIH and back down to VIL. 6. The VPP is lowered to VIL. 7. After a delay of at least 1sec minimum, the VPP is raised to VIH. 8. OE is raised to VIH. 9. EPM is raised to VIH. 10. The device now operates in EPROM ARRAY READ/WRITE mode. See Figure 8. Note: The delay between edges should be 1sec minimum unless specified in the timing specification in Table 14.
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Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Figure 8. EPROM ARRAY READ/WRITE Mode Entry Functional Timing
VCC 5V 0V VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL
CLEAR
EPM
CE
VPP
CLOCK
OE
PGM
Data (Port 2) XOUT
Not connected Not connected
Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions EPROM Signal D0-D3 D4-D7 GND VCC CE NC OE EPM VPP 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 Pin 7 Pin 6 Pin 8 Pin 9 Pin 10 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Pin 8 Pin 7 Pin 9 Pin 10 Pin 11 Forced State NC NC GND 5V VIL No Connection See Figure 8 See Figure 8 See Figure 8
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Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions (Continued) EPROM Signal CLEAR CLOCK PGM 18-Pin DIP/SOIC Pin 11 Pin 12 Pin 13 20-Pin SSOP Pin 12 Pin 13 Pin 14 Forced State See Figure 8 VIL VIH
EPROM ARRAY READ Mode Operation 1. Perform Steps 1 through 6 of the EPROM ARRAY READ/WRITE mode entry (see the EPROM ARRAY READ/WRITE Mode Entry operation, previous page) before proceeding to Step 2. 2. Reset the address counter by pulsing the CLEAR pin. See Figure 9 and Table 8. Please refer to Table 14 for minimum and maximum widths of the CLOCK and CLEAR signals. 3. The address counter is incremented on the rising edge of the CLOCK signal. 4. After resetting the address counter using the CLEAR pin, the address counter points to address 0000h. 5. The READ operation is performed by lowering OE to VIL and reading the data on Port2. Pins P20 to P27 represent the EPROM data D0 to D7, respectively. See Figure 9 and Table 8. 6. A VOH-level READ on Port2 corresponds to a 1 state, while a VOL level corresponds to a 0 level stored in the EPROM array. Note: Please refer to Table 14 for the minimum and maximum width of OE during EPROM READ mode and data access time. 7. The next address is read by pulsing the clock pin High, then forcing OE to VIL and bringing it back High after the data is read. 8. Repeat Step 7 until the final address is read. 9. Because the address is sequentially accessed, a previously-accessed address can only be read by resetting the address counter to 0000h and clocking the address counter to increment to the appropriate address.
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Figure 9. EPROM ARRAY READ Mode Functional Timing
V CC
CLEAR EPM CE VPP CLOCK OE PGM Data (Port 2) Internal Address
5V 0V VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL
Invalid
Data Out
Invalid
Data Out
Invalid
0000h
0001h
0002h
XOUT
Not connected
Table 8. EPROM ARRAY READ Mode Conditions EPROM Signal D0-D3 D4-D7 GND VCC CE NC OE EPM VPP 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 Pin 7 Pin 6 Pin 8 Pin 9 Pin 10 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Pin 8 Pin 7 Pin 9 Pin 10 Pin 11 Forced State See Figure 9 See Figure 9 GND 5V VIL No Connection See Figure 9 VIH VIH
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Table 8. EPROM ARRAY READ Mode Conditions (Continued) CLEAR CLOCK PGM Pin 11 Pin 12 Pin 13 Pin 12 Pin 13 Pin 14 See Figure 9 See Figure 9 VIH
EPROM ARRAY PROGRAM AND VERIFY Mode Operation 1. Perform the EPROM ARRAY READ/WRITE mode entry (see the EPROM ARRAY READ/WRITE Mode Entry operation on page 10) before proceeding to Step 2. 2. Reset the address counter by pulsing the CLEAR pin. See Figure 10 and Table 9. Please refer to Table 14 for minimum and maximum widths of the CLOCK signal. 3. The address counter is incremented on the rising edge of the CLOCK signal. 4. After resetting the address counter using the CLEAR pin, the address counter points to address 0000h. 5. The PROGRAM operation is performed by lowering PGM to VIL. See Figure 10. Please refer to Table 14 for minimum and maximum widths of the PGM signal. 6. The PROGRAM operation is complete when PGM is raised back to VIH. 7. The VERIFY operation is performed by lowering OE to VIL and reading the data on Port2. Pins P20 to P27 represent the EPROM data D0 to D7, respectively. 8. A VOH-level READ on Port2 corresponds to a 1 state, while a VOL level corresponds to a 0 level stored in the EPROM array. 9. Please refer to Table 14 for the minimum and maximum width of OE during EPROM Read mode and data access time. 10. If the data read shows that the address location is not yet programmed, then repeat Steps 5 to 7 until the data read shows that the address location is programmed. 11. If the address location is not programmed after the 25th try, then the device is considered failed. 12. If the address location is programmed, then the address location is overprogrammed with three times the total accumulated program time. 13. The next address is accessed by pulsing the CLOCK High to VIH, then Low to VIL.
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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14. Repeat Steps 5 to 12 until the last address is read. 15. Because the address is sequentially accessed, a previously-accessed address can only be programmed or read by resetting the address counter to 0000h and clocking the address counter to increment to the appropriate address.
Figure 10. EPROM ARRAY PROGRAM AND VERIFY Functional Timing
VCC
5V 0V VIH VIL VIH VIL VIH VIL
CLEAR
EPM
CE
VPP
VIH VIL VIH VIL VIH VIL VIH VIL
CLOCK
OE
PGM
3 x N x 1ms
Data (Port 2)
Data In
Data Out
Data In
Internal Address
0000h
0001h
Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions EPROM Signal D0-D3 D4-D7 GND VCC CE 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 Pin 7 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Pin 8 Forced State See Figure 10 See Figure 10 GND 5V VIL
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions (Continued) NC OE EPM VPP CLEAR CLOCK PGM Pin 6 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 7 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 No Connection See Figure 10 VIH VIH See Figure 10 See Figure 10 See Figure 10
Option Bit Modes
Table 10 lists the device's available option bits and their default states.
Table 10. Option Bit Values* Bit D0 D1 D2 D3 D4 D5 D6 D7 Option ROM Protect Low-EMI Mode Autolatches Reserved Permanent WDT Reserved RC Oscillator 32-kHz Oscillator Unprogrammed Default Value Disabled Disabled Enabled Must be 1 Disabled Must be 1 Disabled Disabled
Note: Option bits are 0 when programmed and 1 when unprogrammed.
OPTION BIT PROGRAM AND VERIFY Mode Entry 1. To enter OPTION BIT PROGRAM AND VERIFY mode, all pins must be set as per Table 11. The initial state for VPP and CLEAR is VIL while OE is at VIH. 2. VPP is raised to VIH. 3. CLEAR is pulsed High to VIH, then Low to VIL. See Table 14 for specifications regarding the CLEAR signal. 4. VPP is lowered to VIL. 5. After a delay of at least 1s minimum, VPP is raised to VIH.
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Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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6. After a delay of at least 1s minimum from VPP rising, OE is raised to VIH. 7. The CLOCK is raised to VIH. 8. OE is pulsed Low to VIL, then High to VIH. 9. The CLOCK is lowered to VIL. 10. Repeat steps 7 to 9 six more times. 11. After a delay of at least 1s minimum, EPM is raised to VIH. 12. The device is now in OPTION BIT READ/WRITE mode. See Figure 11.
Figure 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Functional Timing
V CC
5V 0V VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL VIH V IL
CLEAR EPM
CE
VPP CLOCK OE PGM
Data (Port 2)
Not connected Not connected
XOUT
Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions EPROM Signal D0-D3 D4-D7 GND VCC 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Forced State NC NC GND 5V
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Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions (Continued) CE NC OE EPM VPP CLEAR CLOCK PGM Pin 7 Pin 6 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 8 Pin 7 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 VIL No Connection See Figure 11 See Figure 11 See Figure 11 See Figure 11 See Figure 11 VIH
OPTION BIT PROGRAM AND VERIFY Mode Operation 1. Perform the Option Bit READ/WRITE Mode Entry operation (see OPTION BIT PROGRAM AND VERIFY Mode Entry on page 16) before proceeding to Step 2. 2. The CLOCK is pulsed High to VIH, then Low to VIL. Please refer to Table 14 for minimum and maximum widths of the CLOCK signal. See Figure 12 and Table 12. 3. The 8 option bit values required in Table 10 are forced onto Port2. Option bits D0 to D7 corresponds to Port2 pins P20 to P27. Please refer to Table 14 for setup and hold times. 4. The PROGRAM operation is performed by lowering PGM to VIL. Please refer to Table 14 for minimum and maximum widths of the PGM signal. See Figure 12 and Table 12. 5. The PROGRAM operation is complete when the PGM is raised back to VIH. 6. The VERIFY operation is performed by lowering OE to VIL, then reading the data on Port2. Pins P20 to P27 represent the Option Bit data D0 to D7, respectively. 7. A VOH-level READ on Port2 corresponds to a 1 state (unprogrammed), while a VOL level corresponds to a 0 level stored in the EPROM array. Note: Please refer to Table 14 for the minimum and maximum width of OE during EPROM READ mode and data access time. 8. If the data read shows that the address location is not yet programmed, then repeat Steps 4 to 7 until the data read shows that the address location is programmed.
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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9. If the address location is not programmed after the 25th try, then the device is failed. 10. If the address location shows that it is programmed, then the address location is then overprogrammed with three times the total accumulated program time.
Figure 12. OPTION BIT PROGRAM AND VERIFY Functional Timing
VCC
5V 0V VIH VIL VIH VIL VIH VIL
CLEAR
EPM
(CE)
VPP
VIH VIL VIH VIL VIH VIL VIH VIL
CLOCK
OE
PGM
3 x N x 1ms
Data (Port 2)
Data In
Data Out
Data In
Data Out
Table 12. OPTION BIT PROGRAM AND VERIFY Mode Conditions EPROM Signal D0-D3 D4-D7 GND VCC CE NC 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 Pin 7 Pin 6 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Pin 8 Pin 7 Forced State See Figure 12 See Figure 12 GND 5V VIL No Connection
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
20
Table 12. OPTION BIT PROGRAM AND VERIFY Mode Conditions (Continued) OE EPM VPP CLEAR CLOCK PGM Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 See Figure 12 VIH VIH See Figure 12 See Figure 12 See Figure 12
OPTION BIT READ Mode Operation 1. Perform the Option Bit READ/WRITE Mode Entry operation (see OPTION BIT PROGRAM AND VERIFY Mode Entry on page 16) before proceeding to Step 2. 2. CLOCK is pulsed High to VIH, then Low to VIL. Please refer to Table 14 for the minimum and maximum width values of the CLOCK signal. 3. The 8 option bit values required in Table 10 are read from Port2. Option bits D0 to D7 correspond to Port2 pins P20 to P27. Please refer to Table 14 for setup and hold times. 4. The OPTION BIT READ operation is performed by lowering OE to VIL and reading the data on Port2. Pins P20 to P27 represent the option bit data D0 to D7, respectively. See Figure 13. 5. A VOH-level READ on Port2 corresponds to a 1 state, while a VOL-level corresponds to a 0 level stored in the EPROM array. 6. Please refer to Table 14 for the minimum and maximum width of OE during EPROM READ mode and data access time.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
21
Figure 13. OPTION BIT READ Mode Functional Timing
VCC
5V 0V
CLEAR VIH IL EPM VIH IL
CE VIH IL
V V
V
VPP V IL CLOCK VIH IL OE VIH IL PGM VIH IL Data (Port 2)
XOUT Not connected Invalid Data Out Invalid
V V V
VIH
Power-Down Procedure
The following steps outline the power-down operation of the Z86E0x device. 1. Set up the I/O pins per Figure 14 and Table 13. 2. CE is raised to VIH. 3. EPM is lowered to GND. 4. VPP is lowered to GND. 5. VCC is lowered from 5.0V to 2.0V. 6. PGM is lowered to GND. 7. OE is lowered to GND. 8. CE is lowered to GND. 9. VCC is lowered to GND.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Figure 14. Power-Down Functional Timing
VCC CLEAR EPM
5V 2V 0V VIH 0V
(CE)
VIH 0V VIH 0V VIH 0V VIH 0V VIH 0V
VPP CLOCK OE PGM
Data (Port 2) XOUT
Not connected Not connected
Table 13. Power-Down Conditions EPROM Signal D0-D3 D4-D7 GND VCC CE NC OE EPM VPP CLEAR CLOCK PGM 18-Pin DIP/SOIC Pins 15, 16, 17, 18 Pins 1, 2, 3, 4 Pin 14 Pin 5 Pin 7 Pin 6 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 20-Pin SSOP Pins 17, 18, 19, 20 Pins 1, 2, 3, 4 Pins 15, 16 Pins 5, 6 Pin 8 Pin 7 Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Forced State NC NC GND See Figure 14 See Figure 14 No Connection See Figure 14 See Figure 14 See Figure 14 VIL VIL See Figure 14
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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EPROM I/O Timing
The following section details the programming and verification of the OTP. Input and output timing is illustrated in Figure 15. Timing specifications are provided in Table 14. Voltage specifications are provided in Table 15.
Figure 15. Z86E0x EPROM ARRAY and OPTION BIT PROGRAM AND VERIFY Waveform*
4 Clock VIH Data VIL 1 Data Stable 5 VIH OE VIL VIH PGM VIL 6 7 Program Cycle Verify Cycle 9 2 8 10 Data Out Valid 12
3 11
Note: *EPROM bits are 0 when programmed, and 1 when unprogrammed.
Table 14. Timing Specifications Parameters 1 2 3 4 5 6 7 Name Address setup time Chip Enable setup time PGM setup time Address to OE setup time Data setup time Program pulse width Overprogram pulse width Min 2 2 2 2 2 0.95 2.85 Max Units s s s s s ms ms
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Table 14. Timing Specifications (Continued) Parameters 8 9 10 11 12 Name Data hold time OE setup time Data access time OE width Data output float time Min 2 2 188 250 100 Max Units s s ns ns ns
Table 15. Voltage Specifications 20C to 30C Symbol VPROG IPROG VIH VIL VOH VOL Description Programming supply voltage Programming supply current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Min 4.75 Max 5.25 50 0.7 x VPROG VPROG+0.3 GND-0.3 VPROG-0.4 1.0 0.2 x VPROG 2.6 1.6 4.8 0.8 Typical 5.0 Unit V mA V V V V
Figure 16 illustrates additional timing for the device. Table 16 provides the timing specifications identified in Figure 16.
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Figure 16. Z86E0x Additional Timing Waveform
T3
CLOCK
T9 T10 T12 T3 T4
T1 T7 T5
CLEAR
OE
T7 T11 T6 T8
Address
0010h
0000h
0001h
0002h
T13
T13
Data
Valid
Valid
Valid
Table 16. Z86E0x Additional Timing Specifications Timing Parameter T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Name CLEAR Width Input CLOCK High Input CLOCK Period Input CLOCK Low CLOCK to Address Counter Out Delay OE Setup Time OE Hold Time OE Width Low CLOCK Falling to CLEAR Rising CLEAR Falling to CLOCK Rising 1s 1s 250ns 2s 2s Minimum 1s 1s 2s 1s 15ns Maximum
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Table 16. Z86E0x Additional Timing Specifications (Continued) Timing Parameter T11 T12 T13 Name CLEAR to Address Counter Out Delay CLOCK Rising to OE Falling Data Access Time 1s 188ns Minimum Maximum 15ns
Programming Flow
Figures 17 and 18 illustrate the flow of the EPROM ARRAY PROGRAM, VERIFY, and READ operations. Figures 19 and 20 illustrate the flow of the OPTION BIT PROGRAM, VERIFY, and READ operations.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
27
Figure 17. EPROM ARRAY PROGRAM, VERIFY, and READ Algorithm
Start
Power-On Reset VCC = 5.0V Send Unlock Sequence and Mode A Select
Clear Address Counter to First Location
N=0
Program 1 ms Pulse
Increment N
N = 25? No
Fail
Yes
Verify One Byte
Pass
Verify Byte
Pass
Fail
Program One Pulse 3xN ms Duration
Increment Address
No
Final Address?
Yes
Clear Address Counter to First Location
EPROM Read One Byte
Pass
Fail
Increment Address
No
Device Failed Final Address?
Yes
Device Passed
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Figure 18. EPROM ARRAY READ Algorithm
Start
Power-On Reset VCC = 5.0V Send Unlock Sequence and Mode A Select
Clear Address Counter to First Location
EPROM Verify One Byte
Pass
Fail
Increment Address
No
Final Address?
Yes
Device Failed
Device Passed
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
29
Figure 19. OPTION BIT PROGRAM, VERIFY, and READ Algorithm
Start
Power-On Reset VCC = 5.0V Send Unlock Sequence and Mode B Select
N=0
Program 1 ms Pulse*
Increment N
N = 25? No
Fail
Yes
Verify One Byte
Pass
Verify Byte
Pass
Fail
Program One Pulse 3xN ms Duration
Device Failed Device Passed
Note: *It is assumed that the user has already selected the option bits prior to this step.
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
30
Figure 20. OPTION BIT READ Algorithm
Start
Power-On Reset VCC = 5.0V Send Unlock Sequence and Mode B Select
Option Bit Verify One Byte*
Pass
Fail
Device Failed Device Passed
Note: *It is assumed that the user has already selected the option bits prior to this step.
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
31
Recommendations to Third-Party Programmers
ZiLOG recommends the top-level flow illustrated in Figure 21 for programming user code and option bits into OTP.
Figure 21. Third-Party Top-Level Algorithm
Start
Download User Code to Buffer
Select Option Bits
EPROM ARRAY PROGRAM/VERIFY User Code
Pass
Fail
Show as Fail
EPROM READ User Code
Pass
Fail
OPTION BIT PROGRAM/VERIFY
Pass
Fail
Show as Pass
ZiLOG recommends that third-party programmers offer the following features for OTP operations.
* * * * *
Blank check Examine OTP code Program/verify code and option bits Verify code Checksum of OTP
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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* * *
Checksum of buffer/RAM Program option bits as a sole option Read option bits as a sole option
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues.
ZiLOG, Inc. 910 East Hamilton Avenue, Suite 110 Campbell, CA 95008 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www.zilog.com
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Programming Specification
Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers
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Third Party Developer Feedback Form
The Z86E02/E04/E08/E09 SL1995 Programming Specification
If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions!
Third Party Developer Information
Name Company Address City/State/Zip Country Phone Fax E-Mail
Third Party Developer Product Information
Serial # or Board Fab #/Rev. # Software Version Document Number Host Computer Description/Type
Return Information
ZiLOG Worldwide Customer Support Center 4201 Bee Caves Road, Suite C-100 Austin, TX, USA 78746 Phone: 1-877-945-6427 Fax: (512) 306-4042 Email: customerfeedback@zilog.com
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________
PS009201-0301
Programming Specification

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